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dc.contributor.authorLe Roux, Rikus
dc.contributor.authorVan Schoor, George
dc.contributor.authorVan Vuuren, Pieter
dc.date.accessioned2017-02-22T10:54:40Z
dc.date.available2017-02-22T10:54:40Z
dc.date.issued2012
dc.identifier.citationLe Roux, R. et al. 2012. Block RAM implementation of a reconfigurable real-time PID controller. IEEE 14th International Conference on High Performance Computing and Communications, 25-27 June. Article no 6332339:1383-1390. [http://ieeexplore.ieee.org/document/6332339/]en_US
dc.identifier.isbn978-1-4673-2164-8
dc.identifier.isbn978-0-7695-4749-7 (Online)
dc.identifier.urihttp://hdl.handle.net/10394/20481
dc.identifier.urihttp://dx.doi.org/10.1109/HPCC.2012.203
dc.identifier.urihttp://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6332339
dc.description.abstractDespite the numerous advantages reconfigurable computing adds to a system, it is only advantageous if the execution time exceeds the configuration time. As a result of the long configuration time, reconfiguration is only suitable for quasi-static applications. Due to the additional overhead required for communication, the bus-based architectures most commonly used to connect the configuration controller to the memory contribute to the configuration time. A method proposed to ameliorate this overhead is an architecture utilizing localized block RAM (BRAM), directly connected to the configuration controller to store the configuration data. The drawback of this method is that the BRAM is extremely limited and only a discrete set of configurations can be stored. This paper is a work in progress and proposes a hardware reconfiguration architecture that addresses the size limitation of the localized BRAM-architecture by using parameterizable configuration. This will allow a single bitstream stored in the BRAM to be specialized according to certain parameters, which will be used to reconfigure the device. This will migrate reconfigurable computing to more dynamic applications. The architecture proposed in this paper will be validated using real-time PID control of a five degree of freedom active magnetic bearing systemen_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectBRAMen_US
dc.subjectFPGAen_US
dc.subjectReconfigurationen_US
dc.subjectPIDen_US
dc.subjectReal-timeen_US
dc.subjectControlen_US
dc.titleBlock RAM implementation of a reconfigurable real-time PID controlleren_US
dc.typePresentationen_US
dc.contributor.researchID12134457 - Van Schoor, George
dc.contributor.researchID10732926 - Van Vuuren, Pieter Andries
dc.contributor.researchID13077643 - Le Roux, Ronnie Rikus


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