dc.contributor.author | Pienaar, Jacques A. | |
dc.contributor.author | Helberg, A.S.J. | |
dc.date.accessioned | 2017-02-07T08:41:24Z | |
dc.date.available | 2017-02-07T08:41:24Z | |
dc.date.issued | 2008 | |
dc.identifier.citation | Pienaar, J.A. & Helberg, A.S.J. 2008. Regenerator for Varshamov-tenengolts-like synchronisation error correcting codes. IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering, SIBIRCON 2008, 21-25 July. [https://doi.org/10.1109/SIBIRCON.2008.4602630] | en_US |
dc.identifier.isbn | 978-1-4244-2133-6 | |
dc.identifier.uri | http://hdl.handle.net/10394/20167 | |
dc.identifier.uri | https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4602630 | |
dc.identifier.uri | https://doi.org/10.1109/SIBIRCON.2008.4602630 | |
dc.description.abstract | Synchronisation errors, that is, the insertion of additional or deletion of valid symbols, are the most difficult class of errors to correct - containing the class of additive errors as a subset. A regenerating algorithm, the core of a channel demodulator, was developed for a class of synchronisation error correcting codes. This class of synchronisation error correcting codes is a generalisation of the code originally developed by R.R. Varshamov and G.M. Tenengolts. In this article two designs are provided for a regenerator of this general class of synchronisation error correcting codes. This design has been successfully implemented and tested on a General Purpose Computer (GPC) and a Field Programmable Gated Array (FPGA) | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.subject | Synchronisation | en_US |
dc.subject | Demodulators | en_US |
dc.subject | Error correction codes | en_US |
dc.subject | Field programmable gate arrays | en_US |
dc.title | Regenerator for Varshamov-tenengolts-like synchronisation error correcting codes | en_US |
dc.type | Presentation | en_US |
dc.contributor.researchID | 12363626 - Helberg, Albertus Stephanus Jacobus | |