impact on the quality of the injected currents

The increasing share of single-phase distributed generation units in low-voltage grids causes voltage unbalance problems and overvoltages. Therefore, the need for power quality improving control strategies of grid-connected inverters emerges. Some control strategies require three-phase four-wire inverter topologies. The simplest way to connect the fourth wire is by connecting it to the mid-point of the dc-bus. This sometimes causes challenges in the stabilisation of the mid-point. In this article, two algorithms for stabilising the midpoint of a three-phase four-wire inverter are proposed. Both algorithms are described in detail and validated experimentally. The results showed that both algorithms perform well under perturbations and are able to maintain the midpoint potential close to zero, while the quality of the injected currents is not deteriorated.


I. INTRODUCTION
The continuous increase of small distributed generation units connected to low voltage distribution grids already have a negative impact on the power quality such as overvoltages, voltage unbalance and increase of voltage waveform distortions.Many control strategies that are able to mitigate voltage unbalance were developed but their main disadvantage is that they impact only the negative-sequence component while the zero-sequence component remains.In [1], an inverter-based control algorithm named three-phase damping control strategy is proposed that is able to mitigate voltage unbalance by emulating a resistive behaviour towards the zero-and the negative-sequence voltage components.The control strategy relies on local measurements at the inverter terminals and reacts very fast to perturbations (in the order of one grid cycle).In [2,3] the same control strategy was extended with a drooping controller that determines the injected active power based on the rms value of the grid voltage.The study showed that the penetration level of renewables can be increased while maintaining the power quality within the prescribed limits by the standard EN50160 [4].Therefore, control strategies that are able to improve the power quality become more attractive.In order to have an impact on the zero-sequence voltage component, these control strategies are interfaced to the grid via a three-phase four wire inverter where the neutral is formed via additional hardware such as capacitors, inductors, semiconductor switches or a combination.However, the neutral point drifts from its original value due to circulating currents, common-mode currents, neutral currents and other perturbations.This leads to the increase of harmonic distortion of the injected currents, possible dc component injection and the malfunction of the inverter.Therefore, keeping the midpoint stable is of great importance.For multi-level neutral point clamped inverters, solutions based on space vector modulation are proposed in literature [5,6].Unfortunately, these inverters require complex control and this makes them less attractive for low voltage DG units.On the other hand, the two-level neutral point clamped inverter topologies are less complex but maintaining the midpoint potential requires additional hardware [5,6,7].Fig. 1 a) and b) depict two state-of-the-art topologies that are able to maintain the potential of the midpoint actively.The disadvantages of both topologies are the additional power-electronic leg and also its control.Therefore, it is better to keep the control complexity and the inverter topology as little as possible.Consequently, the additional switches and complex modulation strategy can be avoided, therefore, the topology depicted in Fig. 1  c) is preferred due to its simplicity.In this article the topology shown in Fig. 1 c) is used and two software solutions that are able to maintain the voltage potential of C 1 and C 2 equal are proposed and maintain the midpoint potential equal to zero.This paper is organized as follows.In Section II a detailed description on the operation of the three-phase damping control strategy is given.In Section III the proposed midpoint control algorithms are mathematically described and the open loop transfer functions are extracted.In Section IV the proposed control algorithms are experimentally validated on a three-phase four-wire inverter equipped with the three-phase damping control strategy.In the last section some conclusions are drawn.

II. THREE-PHASE DAMPING CON-TROL STRATEGY
The three-phase damping control strategy is used to experimentally validate the proposed control algorithms for maintaining the midpoint potential.In order to mitigate the voltage unbalance, the three-phase damping control strategy injects more current in the phase with the lowest voltage and less currents in the phases with the highest voltage.This can result in high neutral current that can further shift the midpoint potential and it can be used to validate the proposed algorithms.

Mathematical description
Harmonic distortions of the voltage waveforms will not be considered in this paper.The phase currents can be written as: where υ a , υ b and υ c are the phase voltages, θ a , θ b and θ c are the respective phase angles, g d is the damping conductance and g 1 is the input conductance.The terms in (1) related to g 1 can be interpreted as the steady-state value of the fundamental component of the injected current.These terms are adapted by the dc-bus voltage controller in order to balance the power exchanged with the grid.Since the dc-bus voltage controller is slow, g 1 is slowly varying.The terms related to g d emulate the resistive behaviour towards the zero-and negativesequence voltage components.

Block diagram
The used control strategy is interfaced to the grid as shown in Fig. 2 and the block diagram of the three-phase damping control strategy is depicted in Fig. 3.The power balance is maintained by the dc-bus voltage controller and its out-put signal g 1 is the fundamental input conductance.All phase voltages υ g , a , υ g , b and υ g , c are normalised and passed to a phase locked loop (PLL) extracts the phase voltage magnitude and the phase angle υ a , θ a , υ b , θ b , υ c and θ c .The damping conductance g d sets the resistive behaviour of the inverter [2,3].These signals and PI controllers calculate the needed action to zero the error between the reference and the measured value.Since the PI controller has poor performance in tracking second order reference signals its output is added to a duty ratio feed-forward block [8].The output of this block is used to generate the driving signals for the semiconductor switches.The dc-bus controller is sampled with 100 Hz sampling frequency while the current controller is sampled with 20 kHz.The dc-bus controller ensures the power balance between the ac and the dc side and it also maintains the dc-bus voltage to enable current injection into the grid [9].The power balance between the ac and the dc side can be written as: where, p 1 (t) is the power of the fundamental component, υ g , x and i g , x are the respective phase voltages and currents L x and L n are the differential filter inductances for the corresponding phase and neutral inductor, respectively.By replacing the phase currents with the corresponding input conductance g x (t), then the power balance equation can be written as: where η is the efficiency of the power electronic inverter, C dc is the dc-bus capacitor value and υ dc (t) is the instantaneous value of the dc-bus voltage.Knowing that: and with the phase voltage equal to: The small signal model can now be obtained after substituting ( 4) and ( 5) in ( 3) and simplifying it to (6): Eq. ( 6) can be expressed in the Laplace domain as follow: Further simplification to: where ĝ tot= ĝ a + ĝ b + ĝ c is the total input conductance and τ=ηV dc C dc /3V rms .The open loop transfer function in the z-domain becomes: The sampling time of this PI controller is 10ms and it calculates its new output value at every zero crossing of phase a.

III. MIDPOINT STABILISATION Split dc-bus controller
The first solution is depicted in Fig. 4a) and it uses two identical dc-bus controllers to maintain the equilibrium between υ C1 and υ C2 .A detailed block diagram of this algorithm is shown in Fig. 3.In this diagram only one of the phases is depicted but the principle is the same as the other two phases.The output of the dc-bus controllers are g 1,n and g 1,p where the first one is used to determine the negative half-sine and the other the positive half sine of the reference currents.The output of the two controllers is passed to a multiplexer that switches between g 1,n and g 1,p depending on the output of the sign detector.A sign detector block generates its output state based on the zero-crossing of the synchronised PLL signal for the respective phase.The total input conductance g 1,tot , to- gether with the other signals voltage magnitudes and phase angles, are used to calculate the magnitude of the reference currents.Index "x" represents the respective reference phase current.The rest of the control algorithm is the same as shown in Fig. 3. From ( 2) and ( 7) it can be seen that the power balance depends on the rms value of the grid voltage V rms .
Therefore, the open loop transfer function for each controller will be the same as ( 8) and ( 9).

Reference current offset
The second solution, is proposed in Fig. 4 b) and a simplified block diagram shown is in Fig. 6.This algorithm uses only one dc-bus voltage controller to ensure the power balance between dc and ac side and a second controller that maintains the difference between υ C1 and υ C2 to be zero.If for example υ C1 >υ C2 , then the midpoint offset controller will add a small positive offset to all reference currents and the voltage difference will be restored to zero.The mathematical expression can be written as: where i comp is the needed offset current.Then taking into account the difference between the capacitor voltages Δυ dc =υ C1 -υ C2 yields to: The open loop transfer function can now be derived: This leads to the same transfer function as (8) but the time constant is different as well as the sampling frequency which is 20kHz.It is assumed that current controllers are working perfectly such that the measured current tracks the reference current perfectly.

IV. EXPERIMENTAL VALID-ATION
The experimental validation of the proposed control algorithms for midpoint balancing is presented in Fig. 7.The three-phase four-wire inverter is connected to a three-phase programmable voltage source via a power analyser and a cable.More information about the setup parameters can be found in Table 1.The programmable voltage source is able to deliver asymmetrical voltages which forces the three-phase damping control strategy to inject asymmetrical currents.The proportional and integral coefficients used for the PI controllers used in the setup are listed in Table 2.The measured waveforms of the phase voltages and the dc-bus voltages at the inverter terminals are shown in Fig. 8.As can be seen the positive and negative dc-bus     Waveforms of the input conductance g 1 and the compensating current i comp needed for the reference current offset are depicted in Fig. 11.For better visualisation, the compensating current is multiplied with a factor of 100.From the obtained experimental measurements listed in Table 3, it can be seen that the rms values of the phase voltages, phase currents, neutral current and the power factors are almost equal when comparing the two algorithms.Although the reference current algorithm injects a slightly higher neutral current the performance of both algorithms is very similar.The harmonic content of the injected currents is also similar.THD is slightly better when the split dc-bus controller is used but overall both algorithms manage to keep the THD below 5% as required by the standard IEC 61000-3-2 [10].The main difference between the proposed algorithms is that the split dc-bus injects a slightly higher magnitude of even harmonics but overall the performance of both algorithms is very similar.Both algorithms are studied up to the 5 th harmonic because the higher order current harmonics have insignificant contribution to the THD of the injected currents.In Table 3, the IEC 61000-3-2 limit values for harmonic currents [10] are compared to the measured values it was found out to be lower in order of magnitude.The last comparison is related to the injection of a dc current.According to [10] the injection of the dc current must be limited to 1% of the nominal current of the inverter.The nominal inverter current is 5.1A (in case of balanced conditions) and the absolute value of the dc current injection from both algorithms does not exceed 40mA which is an excellent key performance indicator.

CONCLUSIONS
Two different control algorithms for stabilising the midpoint voltage of a three-phase four-wire inverter with split dc-bus capacitor are proposed.Both algorithms were analysed and the performance then validated against the same conditions in a controllable experimental environment.It was found that both algorithms are able to maintain the midpoint potential stable while the quality of the injected currents is kept within the limits set by IEC 61000-3-2 [10].

Fig. 2
Fig. 2 Block diagram of a three-phase four-wire inverter with a split dc link capacitor are used for the calculation of the reference currents i a , i b and i c in the reference current former blocks.The calculated reference currents are added to the measured currents i L,a , i L,b and i L,cand PI controllers calculate the needed action to zero the error between the reference and the measured value.Since the PI controller has poor performance in tracking second order reference signals its output is added to a duty ratio feed-forward block[8].The output of this block is used to generate the driving signals for the semiconductor switches.The dc-bus controller is sampled with 100 Hz sampling frequency while the current controller is sampled with 20 kHz.The dc-bus controller ensures the power balance between the ac and the dc side and it also maintains the dc-bus voltage to enable current injection into the grid[9].The power balance between the ac and the dc side can be written as:

Fig. 3
Fig. 3 Block diagram on the tree-phase damping control strategy

Fig. 4
Fig. 4 Midpoint stabilization a) by using split dc-bus controller and b) by offsetting the reference currents

Fig. 8
Fig. 8 Phase voltages and DC-bus voltages ant the inverter terminals

Table 3
Obtained measurements under unbalanced current injection